// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  hva_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Version       :  1.0
// Date          :  HVA
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// ******************************************************************************

#ifndef HVA_C_UNION_DEFINE_H
#define HVA_C_UNION_DEFINE_H

/* Define the union csr_hva_fpga_ver_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_fpga_ver : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_fpga_ver_u;

/* Define the union csr_hva_emu_ver_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_emu_ver : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_emu_ver_u;

/* Define the union csr_hva_mem_attr_win0_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win0_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win0_l_u;

/* Define the union csr_hva_mem_attr_win0_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win0_h : 4; /* [3:0] */
        u32 rsv_0 : 28;              /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win0_h_u;

/* Define the union csr_hva_mem_attr_win1_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win1_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win1_l_u;

/* Define the union csr_hva_mem_attr_win1_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win1_h : 4; /* [3:0] */
        u32 rsv_1 : 28;              /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win1_h_u;

/* Define the union csr_hva_mem_attr_win2_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win2_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win2_l_u;

/* Define the union csr_hva_mem_attr_win2_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win2_h : 4; /* [3:0] */
        u32 rsv_2 : 28;              /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win2_h_u;

/* Define the union csr_hva_mem_attr_win3_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win3_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win3_l_u;

/* Define the union csr_hva_mem_attr_win3_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_win3_h : 4; /* [3:0] */
        u32 rsv_3 : 28;              /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_win3_h_u;

/* Define the union csr_hva_mem_attr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_mem_attr_rd : 5; /* [4:0] */
        u32 rsv_4 : 3;           /* [7:5] */
        u32 hva_mem_attr_wr : 5; /* [12:8] */
        u32 rsv_5 : 19;          /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_mem_attr_u;

/* Define the union csr_hva_ar_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_arqos_set : 4;     /* [3:0] */
        u32 cfg_arssv_set : 1;     /* [4] */
        u32 cfg_arstrmid_mode : 1; /* [5] */
        u32 rsv_6 : 2;             /* [7:6] */
        u32 cfg_rdcln_thrld : 4;   /* [11:8] */
        u32 cfg_rdfna_thrld : 4;   /* [15:12] */
        u32 cfg_rdtype_thrld : 4;  /* [19:16] */
        u32 cfg_rdfa_thrld : 4;    /* [23:20] */
        u32 cfg_rd_fa_mode : 2;    /* [25:24] */
        u32 cfg_rd_fna_mode : 2;   /* [27:26] */
        u32 cfg_rd_cln_mode : 1;   /* [28] */
        u32 cfg_rd_type_mode : 1;  /* [29] */
        u32 rsv_7 : 2;             /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_ar_cfg_u;

/* Define the union csr_hva_wr_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_awqos_set : 4;     /* [3:0] */
        u32 cfg_awssv_set : 1;     /* [4] */
        u32 cfg_awstrmid_mode : 1; /* [5] */
        u32 rsv_8 : 2;             /* [7:6] */
        u32 cfg_wr_so_set : 4;     /* [11:8] */
        u32 cfg_wrfna_thrld : 4;   /* [15:12] */
        u32 cfg_wrtype_thrld : 4;  /* [19:16] */
        u32 cfg_wrfa_thrld : 4;    /* [23:20] */
        u32 cfg_wr_fa_mode : 2;    /* [25:24] */
        u32 cfg_wr_fna_mode : 2;   /* [27:26] */
        u32 cfg_wr_fp_mode : 2;    /* [29:28] */
        u32 cfg_wr_type_mode : 1;  /* [30] */
        u32 cfg_wr_so_mode : 1;    /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_wr_cfg_u;

/* Define the union csr_hva_arstrmid_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_rd_strmid : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_arstrmid_u;

/* Define the union csr_hva_awstrmid_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_wr_strmid : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_awstrmid_u;

/* Define the union csr_hva_peh_enum_bar0_wr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_peh_enum_bar0_wr_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_peh_enum_bar0_wr_mask_u;

/* Define the union csr_hva_peh_enum_bar1_wr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_peh_enum_bar1_wr_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_peh_enum_bar1_wr_mask_u;

/* Define the union csr_hva_peh_enum_bar2_wr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_peh_enum_bar2_wr_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_peh_enum_bar2_wr_mask_u;

/* Define the union csr_hva_peh_enum_bar3_wr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_peh_enum_bar3_wr_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_peh_enum_bar3_wr_mask_u;

/* Define the union csr_hva_peh_enum_bar4_wr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_peh_enum_bar4_wr_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_peh_enum_bar4_wr_mask_u;

/* Define the union csr_hva_peh_enum_bar5_wr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_peh_enum_bar5_wr_mask : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_peh_enum_bar5_wr_mask_u;

/* Define the union csr_hva_peh_feature_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_peh_feature_en : 16; /* [15:0] */
        u32 hva_flr_done : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_peh_feature_en_u;

/* Define the union csr_hva_pf_cmd_type_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pf_cmd_type : 16; /* [15:0] */
        u32 rsv_9 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_pf_cmd_type_u;

/* Define the union csr_hva_int_starus_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_npq_ov_int_status : 1;         /* [0] */
        u32 hva_npq_uf_int_status : 1;         /* [1] */
        u32 hva_npq_send_empty_int_status : 1; /* [2] */
        u32 hva_pq_ov_int_status : 1;          /* [3] */
        u32 hva_pq_uf_int_status : 1;          /* [4] */
        u32 hva_pq_send_empty_int_status : 1;  /* [5] */
        u32 hva_1bit_ecc_int_status : 1;       /* [6] */
        u32 hva_2bit_ecc_int_status : 1;       /* [7] */
        u32 hva_flr_int_status : 1;            /* [8] */
        u32 rsv_10 : 23;                       /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_int_starus_u;

/* Define the union csr_hva_int_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_npq_ov_int_en : 1;         /* [0] */
        u32 hva_npq_uf_int_en : 1;         /* [1] */
        u32 hva_npq_send_empty_int_en : 1; /* [2] */
        u32 hva_pq_ov_int_en : 1;          /* [3] */
        u32 hva_pq_uf_int_en : 1;          /* [4] */
        u32 hva_pq_send_empty_int_en : 1;  /* [5] */
        u32 hva_1bit_ecc_int_en : 1;       /* [6] */
        u32 hva_2bit_ecc_int_en : 1;       /* [7] */
        u32 hva_flr_int_en : 1;            /* [8] */
        u32 rsv_11 : 23;                   /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_int_en_u;

/* Define the union csr_hva_int_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_npq_ov_int_set : 1;         /* [0] */
        u32 hva_npq_uf_int_set : 1;         /* [1] */
        u32 hva_npq_send_empty_int_set : 1; /* [2] */
        u32 hva_pq_ov_int_set : 1;          /* [3] */
        u32 hva_pq_uf_int_set : 1;          /* [4] */
        u32 hva_pq_send_empty_int_set : 1;  /* [5] */
        u32 hva_1bit_ecc_int_set : 1;       /* [6] */
        u32 hva_2bit_ecc_int_set : 1;       /* [7] */
        u32 hva_flr_int_set : 1;            /* [8] */
        u32 rsv_12 : 23;                    /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_int_set_u;

/* Define the union csr_hva_int_raw_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_npq_ov_int_raw_status : 1;         /* [0] */
        u32 hva_npq_uf_int_raw_status : 1;         /* [1] */
        u32 hva_npq_send_empty_int_raw_status : 1; /* [2] */
        u32 hva_pq_ov_int_raw_status : 1;          /* [3] */
        u32 hva_pq_uf_int_raw_status : 1;          /* [4] */
        u32 hva_pq_send_empty_int_raw_status : 1;  /* [5] */
        u32 hva_1bit_ecc_int_raw_status : 1;       /* [6] */
        u32 hva_2bit_ecc_int_raw_status : 1;       /* [7] */
        u32 hva_flr_int_raw_status : 1;            /* [8] */
        u32 rsv_13 : 23;                           /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_int_raw_status_u;

/* Define the union csr_hva_axi_err_msk_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_axi_err_msk : 1; /* [0] */
        u32 rsv_14 : 31;         /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_axi_err_msk_u;

/* Define the union csr_hva_axi_max_trans_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rd_max_trans : 8; /* [7:0] */
        u32 cfg_wr_max_trans : 8; /* [15:8] */
        u32 rsv_15 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_axi_max_trans_u;

/* Define the union csr_hva_cpi_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_cpi_10bit_tag_req_en : 1;  /* [0] */
        u32 hva_cpi_10bit_tag_cpl_en : 1;  /* [1] */
        u32 hva_cpi_extended_tag_en : 1;   /* [2] */
        u32 hva_cpi_cpl_timeout_dis : 1;   /* [3] */
        u32 hva_cpi_cpl_timeout_value : 4; /* [7:4] */
        u32 hva_cpi_cfg_mrrs : 3;          /* [10:8] */
        u32 rsv_16 : 1;                    /* [11] */
        u32 hva_cpi_cfg_mps : 3;           /* [14:12] */
        u32 rsv_17 : 1;                    /* [15] */
        u32 hva_link_down : 1;             /* [16] */
        u32 hva_cpi_tx_crd_active_en : 1;  /* [17] */
        u32 rsv_18 : 14;                   /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_cpi_cfg_u;

/* Define the union csr_hva_cpi_crdt_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_cpi_p_hed_crdt : 8;  /* [7:0] */
        u32 hva_cpi_p_dat_crdt : 8;  /* [15:8] */
        u32 hva_cpi_np_hed_crdt : 8; /* [23:16] */
        u32 rsv_19 : 7;              /* [30:24] */
        u32 hva_cpi_crdt_init : 1;   /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_cpi_crdt_cfg_u;

/* Define the union csr_hva_ram_ecc_bypass_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_ram_err_chk_bypass : 1; /* [0] */
        u32 rsv_20 : 31;                /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_ram_ecc_bypass_u;

/* Define the union csr_hva_ram_ecc_err_ins_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_npq_db_ram_cerr_ins_req : 1;     /* [0] */
        u32 hva_npq_db_ram_ucerr_ins_req : 1;    /* [1] */
        u32 hva_pq_db_ram_cerr_ins_req : 1;      /* [2] */
        u32 hva_pq_db_ram_ucerr_ins_req : 1;     /* [3] */
        u32 hva_npq_entry_ram_cerr_ins_req : 1;  /* [4] */
        u32 hva_npq_entry_ram_ucerr_ins_req : 1; /* [5] */
        u32 hva_pq_entry_ram_cerr_ins_req : 1;   /* [6] */
        u32 hva_pq_entry_ram_ucerr_ins_req : 1;  /* [7] */
        u32 rsv_21 : 24;                         /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_ram_ecc_err_ins_u;

/* Define the union csr_hva_fatal_err_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_npq_db_ram_ucerr_fatal_en : 1;    /* [0] */
        u32 hva_pq_db_ram_ucerr_fatal_en : 1;     /* [1] */
        u32 hva_npq_entry_ram_ucerr_fatal_en : 1; /* [2] */
        u32 hva_pq_entry_ram_ucerr_fatal_en : 1;  /* [3] */
        u32 hva_npq_ov_fatal_en : 1;              /* [4] */
        u32 hva_npq_uf_fatal_en : 1;              /* [5] */
        u32 hva_npq_send_empty_fatal_en : 1;      /* [6] */
        u32 hva_pq_ov_fatal_en : 1;               /* [7] */
        u32 hva_pq_uf_fatal_en : 1;               /* [8] */
        u32 hva_pq_send_empty_fatal_en : 1;       /* [9] */
        u32 rsv_22 : 21;                          /* [30:10] */
        u32 hva_fatal_err_en : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_fatal_err_ctrl_u;

/* Define the union csr_hva_inner_crdt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_inner_cpl_data_crdt : 3; /* [2:0] */
        u32 rsv_23 : 1;                  /* [3] */
        u32 hva_inner_send_npq_crdt : 3; /* [6:4] */
        u32 rsv_24 : 1;                  /* [7] */
        u32 hva_inner_send_pq_crdt : 3;  /* [10:8] */
        u32 rsv_25 : 20;                 /* [30:11] */
        u32 hva_inner_crdt_init : 1;     /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_inner_crdt_u;

/* Define the union csr_hva_fifo_af_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_pq_sdata_fifo_af_th : 4; /* [3:0] */
        u32 rsv_26 : 28;                 /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_fifo_af_cfg_u;

/* Define the union csr_hva_bd_cfg_pf_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 bd_cfg_pf_num : 4; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_bd_cfg_pf_num_u;

/* Define the union csr_hva_flr_sta_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_flr_sta : 16; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_flr_sta_u;

/* Define the union csr_hva_dfx_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tx_cpl_stat_en : 1;        /* [0] */
        u32 dfx_tx_cpl_stat_clr : 1;       /* [1] */
        u32 dfx_tx_cpl_cnt_clr : 1;        /* [2] */
        u32 dfx_hva_get_cpi_p_cnt_clr : 1; /* [3] */
        u32 dfx_tx_p_stat_en : 1;          /* [4] */
        u32 dfx_tx_p_stat_clr : 1;         /* [5] */
        u32 hva_dfx_ucerr_cnt_clr : 1;     /* [6] */
        u32 hva_dfx_cerr_cnt_clr : 1;      /* [7] */
        u32 rsv_27 : 24;                   /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_cfg_u;

/* Define the union csr_hva_dfx_cpl_bw0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tx_cpl_bw_curr : 16; /* [15:0] */
        u32 dfx_tx_cpl_bw_max : 16;  /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_cpl_bw0_u;

/* Define the union csr_hva_dfx_cpl_bw1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tx_cpl_bw_ava : 16; /* [15:0] */
        u32 rsv_28 : 16;            /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_cpl_bw1_u;

/* Define the union csr_hva_dfx_npq_db_state_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_npq_db_state : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_npq_db_state_u;

/* Define the union csr_hva_dfx_tx_cpl_cnt0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tx_cpl_dat_err_cnt : 16;   /* [15:0] */
        u32 dfx_tx_cpl_unsuccess_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_tx_cpl_cnt0_u;

/* Define the union csr_hva_dfx_tx_cpl_cnt1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tx_cpl_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_tx_cpl_cnt1_u;

/* Define the union csr_hva_npq_ptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_npq_send_ptr : 8; /* [7:0] */
        u32 dfx_npq_free_ptr : 8; /* [15:8] */
        u32 dfx_npq_rls_ptr : 8;  /* [23:16] */
        u32 dfx_npq_free_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_npq_ptr_u;

/* Define the union csr_hva_dfx_p_bw0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tx_p_bw_curr : 16; /* [15:0] */
        u32 dfx_tx_p_bw_max : 16;  /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_p_bw0_u;

/* Define the union csr_hva_dfx_p_bw1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tx_p_bw_ava : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_p_bw1_u;

/* Define the union csr_hva_dfx_p_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_get_cpi_p_cnt : 16; /* [15:0] */
        u32 rsv_30 : 16;                /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_p_cnt_u;

/* Define the union csr_hva_dfx_pq_ptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_pq_send_ptr : 8; /* [7:0] */
        u32 dfx_pq_free_ptr : 8; /* [15:8] */
        u32 dfx_pq_rls_ptr : 8;  /* [23:16] */
        u32 dfx_pq_free_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_pq_ptr_u;

/* Define the union csr_hva_dfx_pq_wr_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_31 : 16;              /* [15:0] */
        u32 dfx_pq_wr_err_abresp : 1; /* [16] */
        u32 dfx_pq_wr_err : 1;        /* [17] */
        u32 dfx_pq_wr_err_clr : 1;    /* [18] */
        u32 rsv_32 : 13;              /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_pq_wr_err_u;

/* Define the union csr_hva_dfx_pq_wr_err_addr_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_pq_wr_err_addr_h : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_pq_wr_err_addr_h_u;

/* Define the union csr_hva_dfx_pq_wr_err_addr_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_pq_wr_err_addr_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_pq_wr_err_addr_l_u;

/* Define the union csr_hva_dfx_tlp_zero_len_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_pq_zero_write : 1; /* [0] */
        u32 dfx_npq_zero_read : 1; /* [1] */
        u32 rsv_33 : 30;           /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_tlp_zero_len_u;

/* Define the union csr_hva_dfx_axi_bid_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_bid_err : 1; /* [0] */
        u32 rsv_34 : 31;         /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_axi_bid_err_u;

/* Define the union csr_hva_dfx_db_ecc_err_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_dfx_pq_db_ecc_err_addr : 5;  /* [4:0] */
        u32 rsv_35 : 11;                     /* [15:5] */
        u32 hva_dfx_npq_db_ecc_err_addr : 9; /* [24:16] */
        u32 rsv_36 : 7;                      /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_db_ecc_err_addr_u;

/* Define the union csr_hva_dfx_entry_ecc_err_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_dfx_pq_entry_ecc_err_addr : 7;  /* [6:0] */
        u32 rsv_37 : 1;                         /* [7] */
        u32 hva_dfx_npq_entry_ecc_err_addr : 7; /* [14:8] */
        u32 rsv_38 : 17;                        /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_entry_ecc_err_addr_u;

/* Define the union csr_hva_dfx_mem_cerr_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_dfx_mem_cerr_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_mem_cerr_cnt_u;

/* Define the union csr_hva_dfx_mem_ucerr_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_dfx_mem_ucerr_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_mem_ucerr_cnt_u;

/* Define the union csr_hva_dfx_ecc_sta_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_npq_db_ram_cerr : 1;     /* [0] */
        u32 hva_npq_db_ram_ucerr : 1;    /* [1] */
        u32 hva_pq_db_ram_cerr : 1;      /* [2] */
        u32 hva_pq_db_ram_ucerr : 1;     /* [3] */
        u32 hva_npq_entry_ram_cerr : 1;  /* [4] */
        u32 hva_npq_entry_ram_ucerr : 1; /* [5] */
        u32 hva_pq_entry_ram_cerr : 1;   /* [6] */
        u32 hva_pq_entry_ram_ucerr : 1;  /* [7] */
        u32 rsv_39 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_dfx_ecc_sta_u;

/* Define the union csr_hva_op_bar_addr_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_rd_bar_add_err : 1; /* [0] */
        u32 dfx_wr_bar_add_err : 1; /* [1] */
        u32 rsv_40 : 30;            /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_op_bar_addr_err_u;

/* Define the union csr_hva_op_bar_addr_err_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_rd_bar_add_err_cnt : 16; /* [15:0] */
        u32 dfx_wr_bar_add_err_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_op_bar_addr_err_cnt_u;

/* Define the union csr_cpi_hva_req_tlp_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_cpi_hva_p_cnt : 16;  /* [15:0] */
        u32 dfx_cpi_hva_np_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cpi_hva_req_tlp_num_u;

/* Define the union csr_hva_cpi_req_tlp_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_cpi_p_cnt : 16;  /* [15:0] */
        u32 dfx_hva_cpi_np_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_cpi_req_tlp_num_u;

/* Define the union csr_cpl_tlp_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_cpi_hva_cpl_cnt : 16; /* [15:0] */
        u32 dfx_hva_cpi_cpl_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_cpl_tlp_num_u;

/* Define the union csr_hva_smmu_axi_rd_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_smmu_hva_rl_cnt : 16; /* [15:0] */
        u32 dfx_hva_smmu_ar_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smmu_axi_rd_num_u;

/* Define the union csr_hva_smmu_axi_wr_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_smmu_wl_cnt : 16; /* [15:0] */
        u32 dfx_hva_smmu_aw_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smmu_axi_wr_num_u;

/* Define the union csr_hva_axi_b_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_disp_b_cnt : 16; /* [15:0] */
        u32 dfx_smmu_hva_b_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_axi_b_num_u;

/* Define the union csr_disp_hva_axi_rd_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_disp_rl_cnt : 16; /* [15:0] */
        u32 dfx_disp_hva_ar_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_disp_hva_axi_rd_num_u;

/* Define the union csr_disp_hva_axi_wr_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_disp_hva_wl_cnt : 16; /* [15:0] */
        u32 dfx_disp_hva_aw_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_disp_hva_axi_wr_num_u;

/* Define the union csr_hva_cpi_cpl_tnum_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_cpi_cpl_tcnt : 16; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_cpi_cpl_tnum_u;

/* Define the union csr_msi_len_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_msi_len_err : 1; /* [0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_msi_len_err_u;

/* Define the union csr_hva_lat_sts_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lat_stat_clr : 1; /* [0] */
        u32 cfg_lat_stat_en : 1;  /* [1] */
        u32 rsv_41 : 30;          /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_lat_sts_cfg_u;

/* Define the union csr_hva_wr_bp_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_wr_bp_clr_th : 16; /* [15:0] */
        u32 cfg_wr_bp_th : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_wr_bp_cfg_u;

/* Define the union csr_hva_rd_bp_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rd_bp_clr_th : 16; /* [15:0] */
        u32 cfg_rd_bp_th : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_rd_bp_cfg_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_hva_fpga_ver_u hva_fpga_ver;                             /* 0 */
    volatile csr_hva_emu_ver_u hva_emu_ver;                               /* 4 */
    volatile csr_hva_mem_attr_win0_l_u hva_mem_attr_win0_l;               /* C */
    volatile csr_hva_mem_attr_win0_h_u hva_mem_attr_win0_h;               /* 10 */
    volatile csr_hva_mem_attr_win1_l_u hva_mem_attr_win1_l;               /* 14 */
    volatile csr_hva_mem_attr_win1_h_u hva_mem_attr_win1_h;               /* 18 */
    volatile csr_hva_mem_attr_win2_l_u hva_mem_attr_win2_l;               /* 1C */
    volatile csr_hva_mem_attr_win2_h_u hva_mem_attr_win2_h;               /* 20 */
    volatile csr_hva_mem_attr_win3_l_u hva_mem_attr_win3_l;               /* 24 */
    volatile csr_hva_mem_attr_win3_h_u hva_mem_attr_win3_h;               /* 28 */
    volatile csr_hva_mem_attr_u hva_mem_attr[5];                          /* 30 */
    volatile csr_hva_ar_cfg_u hva_ar_cfg;                                 /* 50 */
    volatile csr_hva_wr_cfg_u hva_wr_cfg;                                 /* 54 */
    volatile csr_hva_arstrmid_u hva_arstrmid;                             /* 58 */
    volatile csr_hva_awstrmid_u hva_awstrmid;                             /* 5C */
    volatile csr_hva_peh_enum_bar0_wr_mask_u hva_peh_enum_bar0_wr_mask;   /* 60 */
    volatile csr_hva_peh_enum_bar1_wr_mask_u hva_peh_enum_bar1_wr_mask;   /* 64 */
    volatile csr_hva_peh_enum_bar2_wr_mask_u hva_peh_enum_bar2_wr_mask;   /* 68 */
    volatile csr_hva_peh_enum_bar3_wr_mask_u hva_peh_enum_bar3_wr_mask;   /* 6C */
    volatile csr_hva_peh_enum_bar4_wr_mask_u hva_peh_enum_bar4_wr_mask;   /* 70 */
    volatile csr_hva_peh_enum_bar5_wr_mask_u hva_peh_enum_bar5_wr_mask;   /* 74 */
    volatile csr_hva_peh_feature_en_u hva_peh_feature_en;                 /* 78 */
    volatile csr_hva_pf_cmd_type_u hva_pf_cmd_type;                       /* 7C */
    volatile csr_hva_int_starus_u hva_int_starus;                         /* 80 */
    volatile csr_hva_int_en_u hva_int_en;                                 /* 84 */
    volatile csr_hva_int_set_u hva_int_set;                               /* 88 */
    volatile csr_hva_int_raw_status_u hva_int_raw_status;                 /* 8C */
    volatile csr_hva_axi_err_msk_u hva_axi_err_msk;                       /* 90 */
    volatile csr_hva_axi_max_trans_u hva_axi_max_trans;                   /* A0 */
    volatile csr_hva_cpi_cfg_u hva_cpi_cfg;                               /* B0 */
    volatile csr_hva_cpi_crdt_cfg_u hva_cpi_crdt_cfg;                     /* B4 */
    volatile csr_hva_ram_ecc_bypass_u hva_ram_ecc_bypass;                 /* B8 */
    volatile csr_hva_ram_ecc_err_ins_u hva_ram_ecc_err_ins;               /* BC */
    volatile csr_hva_fatal_err_ctrl_u hva_fatal_err_ctrl;                 /* C0 */
    volatile csr_hva_inner_crdt_u hva_inner_crdt;                         /* C4 */
    volatile csr_hva_fifo_af_cfg_u hva_fifo_af_cfg;                       /* C8 */
    volatile csr_hva_bd_cfg_pf_num_u hva_bd_cfg_pf_num;                   /* CC */
    volatile csr_hva_flr_sta_u hva_flr_sta;                               /* D0 */
    volatile csr_hva_dfx_cfg_u hva_dfx_cfg;                               /* 200 */
    volatile csr_hva_dfx_cpl_bw0_u hva_dfx_cpl_bw0;                       /* 210 */
    volatile csr_hva_dfx_cpl_bw1_u hva_dfx_cpl_bw1;                       /* 220 */
    volatile csr_hva_dfx_npq_db_state_u hva_dfx_npq_db_state;             /* 230 */
    volatile csr_hva_dfx_tx_cpl_cnt0_u hva_dfx_tx_cpl_cnt0;               /* 240 */
    volatile csr_hva_dfx_tx_cpl_cnt1_u hva_dfx_tx_cpl_cnt1;               /* 250 */
    volatile csr_hva_npq_ptr_u hva_npq_ptr;                               /* 260 */
    volatile csr_hva_dfx_p_bw0_u hva_dfx_p_bw0;                           /* 270 */
    volatile csr_hva_dfx_p_bw1_u hva_dfx_p_bw1;                           /* 280 */
    volatile csr_hva_dfx_p_cnt_u hva_dfx_p_cnt;                           /* 290 */
    volatile csr_hva_dfx_pq_ptr_u hva_dfx_pq_ptr;                         /* 2A0 */
    volatile csr_hva_dfx_pq_wr_err_u hva_dfx_pq_wr_err;                   /* 2B0 */
    volatile csr_hva_dfx_pq_wr_err_addr_h_u hva_dfx_pq_wr_err_addr_h;     /* 2C0 */
    volatile csr_hva_dfx_pq_wr_err_addr_l_u hva_dfx_pq_wr_err_addr_l;     /* 2D0 */
    volatile csr_hva_dfx_tlp_zero_len_u hva_dfx_tlp_zero_len;             /* 2E0 */
    volatile csr_hva_dfx_axi_bid_err_u hva_dfx_axi_bid_err;               /* 2F0 */
    volatile csr_hva_dfx_db_ecc_err_addr_u hva_dfx_db_ecc_err_addr;       /* 300 */
    volatile csr_hva_dfx_entry_ecc_err_addr_u hva_dfx_entry_ecc_err_addr; /* 310 */
    volatile csr_hva_dfx_mem_cerr_cnt_u hva_dfx_mem_cerr_cnt;             /* 320 */
    volatile csr_hva_dfx_mem_ucerr_cnt_u hva_dfx_mem_ucerr_cnt;           /* 324 */
    volatile csr_hva_dfx_ecc_sta_u hva_dfx_ecc_sta;                       /* 330 */
    volatile csr_hva_op_bar_addr_err_u hva_op_bar_addr_err;               /* 3A0 */
    volatile csr_hva_op_bar_addr_err_cnt_u hva_op_bar_addr_err_cnt;       /* 3A4 */
    volatile csr_cpi_hva_req_tlp_num_u cpi_hva_req_tlp_num;               /* 3A8 */
    volatile csr_hva_cpi_req_tlp_num_u hva_cpi_req_tlp_num;               /* 3AC */
    volatile csr_cpl_tlp_num_u cpl_tlp_num;                               /* 3B0 */
    volatile csr_hva_smmu_axi_rd_num_u hva_smmu_axi_rd_num;               /* 3B4 */
    volatile csr_hva_smmu_axi_wr_num_u hva_smmu_axi_wr_num;               /* 3B8 */
    volatile csr_hva_axi_b_num_u hva_axi_b_num;                           /* 3BC */
    volatile csr_disp_hva_axi_rd_num_u disp_hva_axi_rd_num;               /* 3C0 */
    volatile csr_disp_hva_axi_wr_num_u disp_hva_axi_wr_num;               /* 3C4 */
    volatile csr_hva_cpi_cpl_tnum_u hva_cpi_cpl_tnum;                     /* 3C8 */
    volatile csr_msi_len_err_u msi_len_err;                               /* 3CC */
    volatile csr_hva_lat_sts_cfg_u hva_lat_sts_cfg;                       /* 400 */
    volatile csr_hva_wr_bp_cfg_u hva_wr_bp_cfg;                           /* 404 */
    volatile csr_hva_rd_bp_cfg_u hva_rd_bp_cfg;                           /* 408 */
} S_hva_reg_REGS_TYPE;

/* Declare the struct pointor of the module hva_reg */
extern volatile S_hva_reg_REGS_TYPE *gophva_regAllReg;

/* Declare the functions that set the member value */
int iSetHVA_FPGA_VER_hva_fpga_ver(unsigned int uhva_fpga_ver);
int iSetHVA_EMU_VER_hva_emu_ver(unsigned int uhva_emu_ver);
int iSetHVA_MEM_ATTR_WIN0_L_hva_mem_attr_win0_l(unsigned int uhva_mem_attr_win0_l);
int iSetHVA_MEM_ATTR_WIN0_H_hva_mem_attr_win0_h(unsigned int uhva_mem_attr_win0_h);
int iSetHVA_MEM_ATTR_WIN1_L_hva_mem_attr_win1_l(unsigned int uhva_mem_attr_win1_l);
int iSetHVA_MEM_ATTR_WIN1_H_hva_mem_attr_win1_h(unsigned int uhva_mem_attr_win1_h);
int iSetHVA_MEM_ATTR_WIN2_L_hva_mem_attr_win2_l(unsigned int uhva_mem_attr_win2_l);
int iSetHVA_MEM_ATTR_WIN2_H_hva_mem_attr_win2_h(unsigned int uhva_mem_attr_win2_h);
int iSetHVA_MEM_ATTR_WIN3_L_hva_mem_attr_win3_l(unsigned int uhva_mem_attr_win3_l);
int iSetHVA_MEM_ATTR_WIN3_H_hva_mem_attr_win3_h(unsigned int uhva_mem_attr_win3_h);
int iSetHVA_MEM_ATTR_hva_mem_attr_rd(unsigned int uhva_mem_attr_rd);
int iSetHVA_MEM_ATTR_hva_mem_attr_wr(unsigned int uhva_mem_attr_wr);
int iSetHVA_AR_CFG_cfg_arqos_set(unsigned int ucfg_arqos_set);
int iSetHVA_AR_CFG_cfg_arssv_set(unsigned int ucfg_arssv_set);
int iSetHVA_AR_CFG_cfg_arstrmid_mode(unsigned int ucfg_arstrmid_mode);
int iSetHVA_AR_CFG_cfg_rdcln_thrld(unsigned int ucfg_rdcln_thrld);
int iSetHVA_AR_CFG_cfg_rdfna_thrld(unsigned int ucfg_rdfna_thrld);
int iSetHVA_AR_CFG_cfg_rdtype_thrld(unsigned int ucfg_rdtype_thrld);
int iSetHVA_AR_CFG_cfg_rdfa_thrld(unsigned int ucfg_rdfa_thrld);
int iSetHVA_AR_CFG_cfg_rd_fa_mode(unsigned int ucfg_rd_fa_mode);
int iSetHVA_AR_CFG_cfg_rd_fna_mode(unsigned int ucfg_rd_fna_mode);
int iSetHVA_AR_CFG_cfg_rd_cln_mode(unsigned int ucfg_rd_cln_mode);
int iSetHVA_AR_CFG_cfg_rd_type_mode(unsigned int ucfg_rd_type_mode);
int iSetHVA_WR_CFG_cfg_awqos_set(unsigned int ucfg_awqos_set);
int iSetHVA_WR_CFG_cfg_awssv_set(unsigned int ucfg_awssv_set);
int iSetHVA_WR_CFG_cfg_awstrmid_mode(unsigned int ucfg_awstrmid_mode);
int iSetHVA_WR_CFG_cfg_wr_so_set(unsigned int ucfg_wr_so_set);
int iSetHVA_WR_CFG_cfg_wrfna_thrld(unsigned int ucfg_wrfna_thrld);
int iSetHVA_WR_CFG_cfg_wrtype_thrld(unsigned int ucfg_wrtype_thrld);
int iSetHVA_WR_CFG_cfg_wrfa_thrld(unsigned int ucfg_wrfa_thrld);
int iSetHVA_WR_CFG_cfg_wr_fa_mode(unsigned int ucfg_wr_fa_mode);
int iSetHVA_WR_CFG_cfg_wr_fna_mode(unsigned int ucfg_wr_fna_mode);
int iSetHVA_WR_CFG_cfg_wr_fp_mode(unsigned int ucfg_wr_fp_mode);
int iSetHVA_WR_CFG_cfg_wr_type_mode(unsigned int ucfg_wr_type_mode);
int iSetHVA_WR_CFG_cfg_wr_so_mode(unsigned int ucfg_wr_so_mode);
int iSetHVA_ARSTRMID_hva_rd_strmid(unsigned int uhva_rd_strmid);
int iSetHVA_AWSTRMID_hva_wr_strmid(unsigned int uhva_wr_strmid);
int iSetHVA_PEH_ENUM_BAR0_WR_MASK_hva_peh_enum_bar0_wr_mask(unsigned int uhva_peh_enum_bar0_wr_mask);
int iSetHVA_PEH_ENUM_BAR1_WR_MASK_hva_peh_enum_bar1_wr_mask(unsigned int uhva_peh_enum_bar1_wr_mask);
int iSetHVA_PEH_ENUM_BAR2_WR_MASK_hva_peh_enum_bar2_wr_mask(unsigned int uhva_peh_enum_bar2_wr_mask);
int iSetHVA_PEH_ENUM_BAR3_WR_MASK_hva_peh_enum_bar3_wr_mask(unsigned int uhva_peh_enum_bar3_wr_mask);
int iSetHVA_PEH_ENUM_BAR4_WR_MASK_hva_peh_enum_bar4_wr_mask(unsigned int uhva_peh_enum_bar4_wr_mask);
int iSetHVA_PEH_ENUM_BAR5_WR_MASK_hva_peh_enum_bar5_wr_mask(unsigned int uhva_peh_enum_bar5_wr_mask);
int iSetHVA_PEH_FEATURE_EN_hva_peh_feature_en(unsigned int uhva_peh_feature_en);
int iSetHVA_PEH_FEATURE_EN_hva_flr_done(unsigned int uhva_flr_done);
int iSetHVA_PF_CMD_TYPE_cfg_pf_cmd_type(unsigned int ucfg_pf_cmd_type);
int iSetHVA_INT_STARUS_hva_npq_ov_int_status(unsigned int uhva_npq_ov_int_status);
int iSetHVA_INT_STARUS_hva_npq_uf_int_status(unsigned int uhva_npq_uf_int_status);
int iSetHVA_INT_STARUS_hva_npq_send_empty_int_status(unsigned int uhva_npq_send_empty_int_status);
int iSetHVA_INT_STARUS_hva_pq_ov_int_status(unsigned int uhva_pq_ov_int_status);
int iSetHVA_INT_STARUS_hva_pq_uf_int_status(unsigned int uhva_pq_uf_int_status);
int iSetHVA_INT_STARUS_hva_pq_send_empty_int_status(unsigned int uhva_pq_send_empty_int_status);
int iSetHVA_INT_STARUS_hva_1bit_ecc_int_status(unsigned int uhva_1bit_ecc_int_status);
int iSetHVA_INT_STARUS_hva_2bit_ecc_int_status(unsigned int uhva_2bit_ecc_int_status);
int iSetHVA_INT_STARUS_hva_flr_int_status(unsigned int uhva_flr_int_status);
int iSetHVA_INT_EN_hva_npq_ov_int_en(unsigned int uhva_npq_ov_int_en);
int iSetHVA_INT_EN_hva_npq_uf_int_en(unsigned int uhva_npq_uf_int_en);
int iSetHVA_INT_EN_hva_npq_send_empty_int_en(unsigned int uhva_npq_send_empty_int_en);
int iSetHVA_INT_EN_hva_pq_ov_int_en(unsigned int uhva_pq_ov_int_en);
int iSetHVA_INT_EN_hva_pq_uf_int_en(unsigned int uhva_pq_uf_int_en);
int iSetHVA_INT_EN_hva_pq_send_empty_int_en(unsigned int uhva_pq_send_empty_int_en);
int iSetHVA_INT_EN_hva_1bit_ecc_int_en(unsigned int uhva_1bit_ecc_int_en);
int iSetHVA_INT_EN_hva_2bit_ecc_int_en(unsigned int uhva_2bit_ecc_int_en);
int iSetHVA_INT_EN_hva_flr_int_en(unsigned int uhva_flr_int_en);
int iSetHVA_INT_SET_hva_npq_ov_int_set(unsigned int uhva_npq_ov_int_set);
int iSetHVA_INT_SET_hva_npq_uf_int_set(unsigned int uhva_npq_uf_int_set);
int iSetHVA_INT_SET_hva_npq_send_empty_int_set(unsigned int uhva_npq_send_empty_int_set);
int iSetHVA_INT_SET_hva_pq_ov_int_set(unsigned int uhva_pq_ov_int_set);
int iSetHVA_INT_SET_hva_pq_uf_int_set(unsigned int uhva_pq_uf_int_set);
int iSetHVA_INT_SET_hva_pq_send_empty_int_set(unsigned int uhva_pq_send_empty_int_set);
int iSetHVA_INT_SET_hva_1bit_ecc_int_set(unsigned int uhva_1bit_ecc_int_set);
int iSetHVA_INT_SET_hva_2bit_ecc_int_set(unsigned int uhva_2bit_ecc_int_set);
int iSetHVA_INT_SET_hva_flr_int_set(unsigned int uhva_flr_int_set);
int iSetHVA_INT_RAW_STATUS_hva_npq_ov_int_raw_status(unsigned int uhva_npq_ov_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_npq_uf_int_raw_status(unsigned int uhva_npq_uf_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_npq_send_empty_int_raw_status(unsigned int uhva_npq_send_empty_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_pq_ov_int_raw_status(unsigned int uhva_pq_ov_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_pq_uf_int_raw_status(unsigned int uhva_pq_uf_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_pq_send_empty_int_raw_status(unsigned int uhva_pq_send_empty_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_1bit_ecc_int_raw_status(unsigned int uhva_1bit_ecc_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_2bit_ecc_int_raw_status(unsigned int uhva_2bit_ecc_int_raw_status);
int iSetHVA_INT_RAW_STATUS_hva_flr_int_raw_status(unsigned int uhva_flr_int_raw_status);
int iSetHVA_AXI_ERR_MSK_hva_axi_err_msk(unsigned int uhva_axi_err_msk);
int iSetHVA_AXI_MAX_TRANS_cfg_rd_max_trans(unsigned int ucfg_rd_max_trans);
int iSetHVA_AXI_MAX_TRANS_cfg_wr_max_trans(unsigned int ucfg_wr_max_trans);
int iSetHVA_CPI_CFG_hva_cpi_10bit_tag_req_en(unsigned int uhva_cpi_10bit_tag_req_en);
int iSetHVA_CPI_CFG_hva_cpi_10bit_tag_cpl_en(unsigned int uhva_cpi_10bit_tag_cpl_en);
int iSetHVA_CPI_CFG_hva_cpi_extended_tag_en(unsigned int uhva_cpi_extended_tag_en);
int iSetHVA_CPI_CFG_hva_cpi_cpl_timeout_dis(unsigned int uhva_cpi_cpl_timeout_dis);
int iSetHVA_CPI_CFG_hva_cpi_cpl_timeout_value(unsigned int uhva_cpi_cpl_timeout_value);
int iSetHVA_CPI_CFG_hva_cpi_cfg_mrrs(unsigned int uhva_cpi_cfg_mrrs);
int iSetHVA_CPI_CFG_hva_cpi_cfg_mps(unsigned int uhva_cpi_cfg_mps);
int iSetHVA_CPI_CFG_hva_link_down(unsigned int uhva_link_down);
int iSetHVA_CPI_CFG_hva_cpi_tx_crd_active_en(unsigned int uhva_cpi_tx_crd_active_en);
int iSetHVA_CPI_CRDT_CFG_hva_cpi_p_hed_crdt(unsigned int uhva_cpi_p_hed_crdt);
int iSetHVA_CPI_CRDT_CFG_hva_cpi_p_dat_crdt(unsigned int uhva_cpi_p_dat_crdt);
int iSetHVA_CPI_CRDT_CFG_hva_cpi_np_hed_crdt(unsigned int uhva_cpi_np_hed_crdt);
int iSetHVA_CPI_CRDT_CFG_hva_cpi_crdt_init(unsigned int uhva_cpi_crdt_init);
int iSetHVA_RAM_ECC_BYPASS_hva_ram_err_chk_bypass(unsigned int uhva_ram_err_chk_bypass);
int iSetHVA_RAM_ECC_ERR_INS_hva_npq_db_ram_cerr_ins_req(unsigned int uhva_npq_db_ram_cerr_ins_req);
int iSetHVA_RAM_ECC_ERR_INS_hva_npq_db_ram_ucerr_ins_req(unsigned int uhva_npq_db_ram_ucerr_ins_req);
int iSetHVA_RAM_ECC_ERR_INS_hva_pq_db_ram_cerr_ins_req(unsigned int uhva_pq_db_ram_cerr_ins_req);
int iSetHVA_RAM_ECC_ERR_INS_hva_pq_db_ram_ucerr_ins_req(unsigned int uhva_pq_db_ram_ucerr_ins_req);
int iSetHVA_RAM_ECC_ERR_INS_hva_npq_entry_ram_cerr_ins_req(unsigned int uhva_npq_entry_ram_cerr_ins_req);
int iSetHVA_RAM_ECC_ERR_INS_hva_npq_entry_ram_ucerr_ins_req(unsigned int uhva_npq_entry_ram_ucerr_ins_req);
int iSetHVA_RAM_ECC_ERR_INS_hva_pq_entry_ram_cerr_ins_req(unsigned int uhva_pq_entry_ram_cerr_ins_req);
int iSetHVA_RAM_ECC_ERR_INS_hva_pq_entry_ram_ucerr_ins_req(unsigned int uhva_pq_entry_ram_ucerr_ins_req);
int iSetHVA_FATAL_ERR_CTRL_hva_npq_db_ram_ucerr_fatal_en(unsigned int uhva_npq_db_ram_ucerr_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_pq_db_ram_ucerr_fatal_en(unsigned int uhva_pq_db_ram_ucerr_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_npq_entry_ram_ucerr_fatal_en(unsigned int uhva_npq_entry_ram_ucerr_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_pq_entry_ram_ucerr_fatal_en(unsigned int uhva_pq_entry_ram_ucerr_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_npq_ov_fatal_en(unsigned int uhva_npq_ov_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_npq_uf_fatal_en(unsigned int uhva_npq_uf_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_npq_send_empty_fatal_en(unsigned int uhva_npq_send_empty_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_pq_ov_fatal_en(unsigned int uhva_pq_ov_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_pq_uf_fatal_en(unsigned int uhva_pq_uf_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_pq_send_empty_fatal_en(unsigned int uhva_pq_send_empty_fatal_en);
int iSetHVA_FATAL_ERR_CTRL_hva_fatal_err_en(unsigned int uhva_fatal_err_en);
int iSetHVA_INNER_CRDT_hva_inner_cpl_data_crdt(unsigned int uhva_inner_cpl_data_crdt);
int iSetHVA_INNER_CRDT_hva_inner_send_npq_crdt(unsigned int uhva_inner_send_npq_crdt);
int iSetHVA_INNER_CRDT_hva_inner_send_pq_crdt(unsigned int uhva_inner_send_pq_crdt);
int iSetHVA_INNER_CRDT_hva_inner_crdt_init(unsigned int uhva_inner_crdt_init);
int iSetHVA_FIFO_AF_CFG_hva_pq_sdata_fifo_af_th(unsigned int uhva_pq_sdata_fifo_af_th);
int iSetHVA_BD_CFG_PF_NUM_bd_cfg_pf_num(unsigned int ubd_cfg_pf_num);
int iSetHVA_FLR_STA_hva_flr_sta(unsigned int uhva_flr_sta);
int iSetHVA_DFX_CFG_dfx_tx_cpl_stat_en(unsigned int udfx_tx_cpl_stat_en);
int iSetHVA_DFX_CFG_dfx_tx_cpl_stat_clr(unsigned int udfx_tx_cpl_stat_clr);
int iSetHVA_DFX_CFG_dfx_tx_cpl_cnt_clr(unsigned int udfx_tx_cpl_cnt_clr);
int iSetHVA_DFX_CFG_dfx_hva_get_cpi_p_cnt_clr(unsigned int udfx_hva_get_cpi_p_cnt_clr);
int iSetHVA_DFX_CFG_dfx_tx_p_stat_en(unsigned int udfx_tx_p_stat_en);
int iSetHVA_DFX_CFG_dfx_tx_p_stat_clr(unsigned int udfx_tx_p_stat_clr);
int iSetHVA_DFX_CFG_hva_dfx_ucerr_cnt_clr(unsigned int uhva_dfx_ucerr_cnt_clr);
int iSetHVA_DFX_CFG_hva_dfx_cerr_cnt_clr(unsigned int uhva_dfx_cerr_cnt_clr);
int iSetHVA_DFX_CPL_BW0_dfx_tx_cpl_bw_curr(unsigned int udfx_tx_cpl_bw_curr);
int iSetHVA_DFX_CPL_BW0_dfx_tx_cpl_bw_max(unsigned int udfx_tx_cpl_bw_max);
int iSetHVA_DFX_CPL_BW1_dfx_tx_cpl_bw_ava(unsigned int udfx_tx_cpl_bw_ava);
int iSetHVA_DFX_NPQ_DB_STATE_dfx_npq_db_state(unsigned int udfx_npq_db_state);
int iSetHVA_DFX_TX_CPL_CNT0_dfx_tx_cpl_dat_err_cnt(unsigned int udfx_tx_cpl_dat_err_cnt);
int iSetHVA_DFX_TX_CPL_CNT0_dfx_tx_cpl_unsuccess_cnt(unsigned int udfx_tx_cpl_unsuccess_cnt);
int iSetHVA_DFX_TX_CPL_CNT1_dfx_tx_cpl_cnt(unsigned int udfx_tx_cpl_cnt);
int iSetHVA_NPQ_PTR_dfx_npq_send_ptr(unsigned int udfx_npq_send_ptr);
int iSetHVA_NPQ_PTR_dfx_npq_free_ptr(unsigned int udfx_npq_free_ptr);
int iSetHVA_NPQ_PTR_dfx_npq_rls_ptr(unsigned int udfx_npq_rls_ptr);
int iSetHVA_NPQ_PTR_dfx_npq_free_cnt(unsigned int udfx_npq_free_cnt);
int iSetHVA_DFX_P_BW0_dfx_tx_p_bw_curr(unsigned int udfx_tx_p_bw_curr);
int iSetHVA_DFX_P_BW0_dfx_tx_p_bw_max(unsigned int udfx_tx_p_bw_max);
int iSetHVA_DFX_P_BW1_dfx_tx_p_bw_ava(unsigned int udfx_tx_p_bw_ava);
int iSetHVA_DFX_P_CNT_dfx_hva_get_cpi_p_cnt(unsigned int udfx_hva_get_cpi_p_cnt);
int iSetHVA_DFX_PQ_PTR_dfx_pq_send_ptr(unsigned int udfx_pq_send_ptr);
int iSetHVA_DFX_PQ_PTR_dfx_pq_free_ptr(unsigned int udfx_pq_free_ptr);
int iSetHVA_DFX_PQ_PTR_dfx_pq_rls_ptr(unsigned int udfx_pq_rls_ptr);
int iSetHVA_DFX_PQ_PTR_dfx_pq_free_cnt(unsigned int udfx_pq_free_cnt);
int iSetHVA_DFX_PQ_WR_ERR_dfx_pq_wr_err_abresp(unsigned int udfx_pq_wr_err_abresp);
int iSetHVA_DFX_PQ_WR_ERR_dfx_pq_wr_err(unsigned int udfx_pq_wr_err);
int iSetHVA_DFX_PQ_WR_ERR_dfx_pq_wr_err_clr(unsigned int udfx_pq_wr_err_clr);
int iSetHVA_DFX_PQ_WR_ERR_ADDR_H_dfx_pq_wr_err_addr_h(unsigned int udfx_pq_wr_err_addr_h);
int iSetHVA_DFX_PQ_WR_ERR_ADDR_L_dfx_pq_wr_err_addr_l(unsigned int udfx_pq_wr_err_addr_l);
int iSetHVA_DFX_TLP_ZERO_LEN_dfx_pq_zero_write(unsigned int udfx_pq_zero_write);
int iSetHVA_DFX_TLP_ZERO_LEN_dfx_npq_zero_read(unsigned int udfx_npq_zero_read);
int iSetHVA_DFX_AXI_BID_ERR_dfx_hva_bid_err(unsigned int udfx_hva_bid_err);
int iSetHVA_DFX_DB_ECC_ERR_ADDR_hva_dfx_pq_db_ecc_err_addr(unsigned int uhva_dfx_pq_db_ecc_err_addr);
int iSetHVA_DFX_DB_ECC_ERR_ADDR_hva_dfx_npq_db_ecc_err_addr(unsigned int uhva_dfx_npq_db_ecc_err_addr);
int iSetHVA_DFX_ENTRY_ECC_ERR_ADDR_hva_dfx_pq_entry_ecc_err_addr(unsigned int uhva_dfx_pq_entry_ecc_err_addr);
int iSetHVA_DFX_ENTRY_ECC_ERR_ADDR_hva_dfx_npq_entry_ecc_err_addr(unsigned int uhva_dfx_npq_entry_ecc_err_addr);
int iSetHVA_DFX_MEM_CERR_CNT_hva_dfx_mem_cerr_cnt(unsigned int uhva_dfx_mem_cerr_cnt);
int iSetHVA_DFX_MEM_UCERR_CNT_hva_dfx_mem_ucerr_cnt(unsigned int uhva_dfx_mem_ucerr_cnt);
int iSetHVA_DFX_ECC_STA_hva_npq_db_ram_cerr(unsigned int uhva_npq_db_ram_cerr);
int iSetHVA_DFX_ECC_STA_hva_npq_db_ram_ucerr(unsigned int uhva_npq_db_ram_ucerr);
int iSetHVA_DFX_ECC_STA_hva_pq_db_ram_cerr(unsigned int uhva_pq_db_ram_cerr);
int iSetHVA_DFX_ECC_STA_hva_pq_db_ram_ucerr(unsigned int uhva_pq_db_ram_ucerr);
int iSetHVA_DFX_ECC_STA_hva_npq_entry_ram_cerr(unsigned int uhva_npq_entry_ram_cerr);
int iSetHVA_DFX_ECC_STA_hva_npq_entry_ram_ucerr(unsigned int uhva_npq_entry_ram_ucerr);
int iSetHVA_DFX_ECC_STA_hva_pq_entry_ram_cerr(unsigned int uhva_pq_entry_ram_cerr);
int iSetHVA_DFX_ECC_STA_hva_pq_entry_ram_ucerr(unsigned int uhva_pq_entry_ram_ucerr);
int iSetHVA_OP_BAR_ADDR_ERR_dfx_rd_bar_add_err(unsigned int udfx_rd_bar_add_err);
int iSetHVA_OP_BAR_ADDR_ERR_dfx_wr_bar_add_err(unsigned int udfx_wr_bar_add_err);
int iSetHVA_OP_BAR_ADDR_ERR_CNT_dfx_rd_bar_add_err_cnt(unsigned int udfx_rd_bar_add_err_cnt);
int iSetHVA_OP_BAR_ADDR_ERR_CNT_dfx_wr_bar_add_err_cnt(unsigned int udfx_wr_bar_add_err_cnt);
int iSetCPI_HVA_REQ_TLP_NUM_dfx_cpi_hva_p_cnt(unsigned int udfx_cpi_hva_p_cnt);
int iSetCPI_HVA_REQ_TLP_NUM_dfx_cpi_hva_np_cnt(unsigned int udfx_cpi_hva_np_cnt);
int iSetHVA_CPI_REQ_TLP_NUM_dfx_hva_cpi_p_cnt(unsigned int udfx_hva_cpi_p_cnt);
int iSetHVA_CPI_REQ_TLP_NUM_dfx_hva_cpi_np_cnt(unsigned int udfx_hva_cpi_np_cnt);
int iSetCPL_TLP_NUM_dfx_cpi_hva_cpl_cnt(unsigned int udfx_cpi_hva_cpl_cnt);
int iSetCPL_TLP_NUM_dfx_hva_cpi_cpl_cnt(unsigned int udfx_hva_cpi_cpl_cnt);
int iSetHVA_SMMU_AXI_RD_NUM_dfx_smmu_hva_rl_cnt(unsigned int udfx_smmu_hva_rl_cnt);
int iSetHVA_SMMU_AXI_RD_NUM_dfx_hva_smmu_ar_cnt(unsigned int udfx_hva_smmu_ar_cnt);
int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_wl_cnt(unsigned int udfx_hva_smmu_wl_cnt);
int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_aw_cnt(unsigned int udfx_hva_smmu_aw_cnt);
int iSetHVA_AXI_B_NUM_dfx_hva_disp_b_cnt(unsigned int udfx_hva_disp_b_cnt);
int iSetHVA_AXI_B_NUM_dfx_smmu_hva_b_cnt(unsigned int udfx_smmu_hva_b_cnt);
int iSetDISP_HVA_AXI_RD_NUM_dfx_hva_disp_rl_cnt(unsigned int udfx_hva_disp_rl_cnt);
int iSetDISP_HVA_AXI_RD_NUM_dfx_disp_hva_ar_cnt(unsigned int udfx_disp_hva_ar_cnt);
int iSetDISP_HVA_AXI_WR_NUM_dfx_disp_hva_wl_cnt(unsigned int udfx_disp_hva_wl_cnt);
int iSetDISP_HVA_AXI_WR_NUM_dfx_disp_hva_aw_cnt(unsigned int udfx_disp_hva_aw_cnt);
int iSetHVA_CPI_CPL_TNUM_dfx_hva_cpi_cpl_tcnt(unsigned int udfx_hva_cpi_cpl_tcnt);
int iSetMSI_LEN_ERR_dfx_msi_len_err(unsigned int udfx_msi_len_err);
int iSetHVA_LAT_STS_CFG_cfg_lat_stat_clr(unsigned int ucfg_lat_stat_clr);
int iSetHVA_LAT_STS_CFG_cfg_lat_stat_en(unsigned int ucfg_lat_stat_en);
int iSetHVA_WR_BP_CFG_cfg_wr_bp_clr_th(unsigned int ucfg_wr_bp_clr_th);
int iSetHVA_WR_BP_CFG_cfg_wr_bp_th(unsigned int ucfg_wr_bp_th);
int iSetHVA_RD_BP_CFG_cfg_rd_bp_clr_th(unsigned int ucfg_rd_bp_clr_th);
int iSetHVA_RD_BP_CFG_cfg_rd_bp_th(unsigned int ucfg_rd_bp_th);


#endif // HI1823_C_UNION_DEFINE_H
